本人(黃世旭教授)主要研究領域為積體電路設計領域，研究範疇包括電子設計自動化、晶片系統設計、低功率邊緣運算等積體電路設計相關議題。自西元 2000 年至本校任教迄今，本人已發表超過三十篇國際期刊論文、五十篇國際會議論文，並取得十個國內外發明專利。
特別值得一提的是，本人長期耕耘於積體電路之時脈訊號 (clock signal) 設計最佳化這個主題，多年來已累積豐碩的成果。自 2003 年我們研究室在重要國際會議 ICCAD (International Conference on Computer Aided Design) 提出結合時脈訊號偏移及加入時間延遲的演算法可以保證達到時序最佳化的下限，我們研究室便一直耕耘時脈訊號設計最佳化這個研究主題，並持續有一系列論文發表於積體電路設計領域重要國際期刊及重要國際會議。
自 2003 年迄今，本人已提出多個新的時脈訊號設計架構(包括相反相位時脈樹架構、型態匹配時脈樹架構、兩電壓階段功率模式感知時脈樹架構)，可以應用於不同的高效能低功率電路設計目標。這些新的時脈樹訊號設計架構，除了論文發表於重要期刊及重要國際會議，並獲得美國發明專利及中華民國發明專利。同時，由於長期耕耘時脈訊號設計最佳化這個研究主題，本人歷年執行的科技部專題研究計畫，亦有多件計畫是與時脈訊號設計最佳化主題相關。
就時脈訊號設計最佳化這個研究主題，本人曾與思源科技、益芯科技、創意電子進行產學合作計畫，並曾技術移轉予益芯科技、創意電子。其中，本人與創意電子的產學合作計畫，是討論先進製程之時脈訊號設計問題。由於先進製程電路尺寸較小，對製程變異所造成的影響很敏感，因此我們發展演算法降低製程變異對時脈訊號的影響，實驗結果顯示我們提出的演算法可有效運用於先進製程。
近年由於人工智慧的快速發展，具有低延遲、即時性的智慧終端系統是產業發展趨勢。因應終端裝置嚴格的尺寸及功率消耗限制，需要針對不同終端裝置去設計其智慧終端系統晶片，才能最小化功率消耗以滿足長時間使用的需求。本人自 2018 年 5 月起參與科技部半導體射月計畫(智慧終端半導體製程與晶片系統研發專案計畫)的執行，進行智慧終端系統晶片之資料路徑子系統設計，在維持人工智慧推論精確度前提下，儘可能減少晶片之功率消耗並提升處理速度。我們研究室期許透過此半導體射月計畫之執行，尋求在人工智慧浪潮中某一點領先全球之定位。
在人才培育方面，本人指導學生參加教育部主辦之積體電路設計相關競賽 (包括積體電路電腦輔助設計軟體製作競賽、智慧電子創新應用與設計競賽)，歷年合計共獲得 3 次特優、1 次優等、5 次佳作。我們研究室目前畢業七十餘名碩士生、五名博士生，目前多在科學園區積體電路設計領域相關公司任職。
在跨校之團隊帶領方面，本人於 2017 ~2020年執行教育部智慧聯網技術與應用人才培育計畫，擔任跨校之「工業物聯網安全及連網整合技術」課程發展計畫的計畫主持人，進行前瞻教材之課程開發及磨課師錄製。本人亦於 2017 ~ 2018 年擔任科技部「AI 創新研究中心專案計畫推動辦公室」共同主持人，協助科技部推動跨領域之AI創新研究及辦理相關配套活動。
本人未來幾年的學術研究發展規劃，預計仍將以「時脈訊號設計最佳化」、「智慧終端系統晶片設計」、「物聯網硬體安全」等主題為主要方向。在人工智慧、物聯網快速發展的時代，我們研究室將持續探討更低耗能、更高速度、更高安全性的晶片設計，以因應積體電路研究發展的趨勢，並培育積體電路產業所需的人才。

很榮幸能獲得本校研究傑出教師獎勵。以下幾點個人經驗與大家分享。
關於研究團隊的建立，本人會鼓勵學生(包括大學部專題生及新進研究生) 參加教育部主辦之積體電路設計相關競賽 (包括積體電路電腦輔助設計軟體製作競賽、智慧電子創新應用與設計競賽)。透過競賽的參與，可增進同學實作能力，並培養團隊合作精神。我們研究室歷年參賽合計共獲得 3 次特優、1 次優等、5 次佳作。比賽獲獎的經驗，也有助增強同學的自信心。
由於電子產業發展日新月異，我們必須隨時留意電子產業的發展趨勢。透過與業界的合作，我們不但可以解決業界需求，也常可以找到新的研究題目。舉例來說，本人近年的產學合作計畫，是討論產業界面臨之時脈訊號設計問題。產學合作計畫之執行，有助我們將學術上的研發成果落實為產業上的實際應用。
長期耕耘於一個主題，比較可以累積豐碩的成果。舉例來說，本人長期耕耘於積體電路之時脈訊號設計最佳化這個主題，並有一系列論文發表於積體電路設計領域重要國際期刊及重要國際會議。由於長期耕耘於此主題，本人在此主題之論文的質與量相對比較凸顯，許多發明專利、研究計畫亦與此主題相關。

My main research area (the main research area of Prof. Shih-Hsu Huang) is in the area of integrated circuit (IC) design, including the aspects of electronic design automation, SoC (system-on-a-chip) design, and low-power edge computing. Since 2000, I have published more than 30 international journal papers and more than 70 international conference papers. Moreover, he has received 10 invention patents.
Especially, I have been devoted to the topic of clock signal design optimization in IC design for many years. In 2003, my laboratory (electronic design automation laboratory) presented a paper in ICCAD (International Conference on Computer Aided Design), which is a top-rated conference in IC design research area. In this paper, we combine clock skew and delay insertion to guarantee achieving the lower bound of timing optimization. Since then, my laboratory has a series of publications in top-rated journals and top-rated conference in IC design area for the topic of clock signal design optimization.
From 2003, I have proposed several novel clock signal design architectures, including opposite-phase clock trees, type-matching clock trees, and two-stage power-mode-aware clock trees, for different low-power high-performance IC design applications. In addition to paper publications, I also obtained patents (including US patents and Taiwan patents) for these inventions. Moreover, since I was dedicated to the topic of clock signal design optimization, I have executed several Taiwan MOST (Ministry of Science and Technology) projects related to this topic.
I also had industry-academia collaboration for the topic of clock signal design optimization. So far, my laboratory had cooperation projects with SpringSoft, CMSC, and GUC (Global Unichip). Moreover, my laboratory had technology transferred to CMSC and GUC. In the cooperation project with GUC, we studied the clock signal design optimization in the advanced process technology. Since the feature size is small, the advanced process technology is sensitive to process variation. Thus, we developed an algorithm to reduce the impact of process variation on clock signal. Experimental results show that the proposed algorithm works well in practice.
As the rapid progress of AI (artificial intelligence), developing real-time edge AI systems is an industry trend. Owing to serious constraints on area and power, there is a demand to customize edge-intelligence SoCs. From May 2018, I am executing Taiwan MOST Moonshot project to perform data path subsystem design for edge-intelligence SoCs. Under a constraint on the inference accuracy, our goal is to minimize the power consumption and maximize the processing speed at the same time. Through the execution of Taiwan MOST Moonshot project, we expect that we can develop world-leading technologies for edge-intelligence SoCs.
I also encourage the students in my laboratory to participate in IC design related competitions each year, including IC CAD (Computer Aided Design) Contest and Intelligent Electronics Innovation Application and Design Competition. These competitions are held by Taiwan MOE (Ministry of Education). So far, my laboratory has received first prize award three times, second prize award one time, and third prize award five times from these competitions. Since 2000, 70 master students and 5 Ph.D. students graduated from my laboratory, and most of them currently work at companies in Scientific Parks.
From 2017 to 2020, I served as the principal investigator (PI) of an MOE project for the development of MOOCs course “Integration Techniques for Industrial IoT (internet of things) Security and Networking”. From 2017 to 2018, I also served as the co-PI of Taiwan MOST project for the Program Office of AI Research to promote AI innovation and research in Taiwan.
In the near future, I will still focus on the topics regarding clock signal design optimization, edge-intelligence SoC design, and IoT hardware security. In the era of AI and IoT, my laboratory will continue to study lower power, higher speed, and more safe IC design technologies to meet industry trends and cultivate talented persons.

It’s my honor to receive the outstanding research faculty award from Chung Yuan Christian University. I have some experiences for sharing below.
I often encourage the students in my laboratory to participate in IC design related competitions, including IC CAD (Computer Aided Design) Contest and Intelligent Electronics Innovation Application and Design Competition. The experiences of competition participation can enhance the implementation skill and the teamwork spirit. So far, my laboratory has received first prize award three times, second prize award one time, and third prize award five times from these competitions. Winning awards can also increase the confidences of students.
Owing to the rapid progress of electronic industry, we need to pay attention to the trend of electronic industry. Through industry-academia collaboration, we not only can solve the problems of the industry, but also can find new research problems. For example, in my recent industry-academia collaboration, we studied the clock signal design optimization problem faced by the industry. The execution of cooperation project can make our research results useful to the industry.
Dedicated to a research topic can help to accumulate research results. For example, I have been devoted to the topic of clock signal design optimization in IC design for many years. Thus, my laboratory has a series of publications in top-rated journals and top-rated conference for the topic of clock signal design optimization. Moreover, I also have many invention patents and research projects related to this research topic.